At present, SDRAMs (Synchronous DRAMs) which are DRAMs (Dynamic Random Access Memories) each operating in synchronization with a clock are used in numerous memory systems. Particularly in recent years, a DDR-SDRAM (Double Date Rate SDRAM) which is a SDRAM having a high-speed data transfer function has received attention. Since the DDR-SDRAM performs data transfer in synchronization with both of a rising edge and a falling edge of a clock, fast data transfer at a speed double the data transfer speed of a conventional SDRAM is possible.
A memory controller in a memory system including a DDR-SDRAM fetches read data from the DDR-SDRAM on a byte-by-byte basis based on the timing of a data strobe signal (DQS) outputted for each set of 1-byte data. For example, when a 32-bit system bus is used, four sets of read data fetched on a byte-by-byte basis are collectively outputted to the outside of the memory system.
When fetching read data from the DDR-SDRAM, in order to normally latch the read data by matching the phases of the DQS and the read data, it is necessary to connect the memory controller and the DDR-SDRAM by effecting equal-length wiring of a data strobe signal line and a data signal line such that a signal arrival time of the DQS from the DDR-SDRAM till it arrives at the memory controller is equal to a signal arrival time of the read data from the DDR-SDRAM till it arrives at the memory controller.
As a technology for equalizing signal arrival times as mentioned above, there has been conventionally known a technology as described in, e.g., Patent Document 1, which provides a delay circuit between a DDR-SDRAM and a semiconductor integrated circuit for controlling the DDR-SDRAM, and adjusts the delay time of a clock and the delay time of a DQS with an access from a CPU provided outside a memory system.
A description will be given hereinbelow to a prior-art technology related to the adjustment of signal arrival times in such a conventional memory system.
FIG. 6 is a block diagram of a principal structure of the conventional memory system. In the drawings, the conventional memory system includes a semiconductor integrated circuit 1 for controlling DDR-SDRAMs, a clock generation circuit 2, the two DDR-SDRAMs 3 and 4, and delay circuits 5, 6, 7, and 8 for delaying signals. In the memory system mentioned above, the delay time of a clock supplied to the DDR-SDRAMs 3 and 4, and the respective delay times of data strobe signals DQS[0] and DQS[1] propagating between the foregoing semiconductor integrated circuit 1 and the foregoing DDR-SDRAMs 3 and 4 are adjusted with an access from a CPU provided outside the memory system. By adjusting the delay times between the data strobe signals DQS[0] and DQS[1] and read data DQ[7:0] and DQ[15:8], the memory system matches the phases of the data strobe signals DQS[0] and DQS[1] and the read data DQ[7:0] and DQ[15:8] which are supplied from the foregoing DDR-SDRAMs 3 and 4 to the semiconductor integrated circuit 1, and smoothly fetches the read data DQ[7:0] and DQ[15:8].
Patent Document 1: Japanese Laid-Open Patent Publication No. H 11-25029